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24AA014H/24LC014H
3.0
FUNCTIONAL DESCRIPTION
4.4
Data Valid (D)
The 24AA014H/24LC014H supports a bidirectional,
2-wire bus and data transmission protocol. A device
that sends data onto the bus is defined as transmitter,
and a device receiving data as receiver. The bus has
to be controlled by a master device that generates the
Serial Clock (SCL), controls the bus access and gen-
erates the Start and Stop conditions while the
24AA014H/24LC014H works as slave. Both master
and slave can operate as transmitter or receiver, but
the master device determines which mode is
activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited, though only the last sixteen will
4.0
BUS CHARACTERISTICS
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in
The following bus protocol has been defined:
first-out fashion.
? Data transfer may be initiated only when the bus
is not busy.
4.5
Acknowledge
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Note:
The 24AA014H/24LC014H does not gen-
erate any Acknowledge bits if an internal
programming cycle is in progress.
4.1
Bus Not Busy (A)
The device that acknowledges has to pull down the
Both data and clock lines remain high.
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
4.2
Start Data Transfer (B)
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the
4.3
Stop Data Transfer (C)
master to generate the Stop condition (Figure 4-2).
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
SCL
(A)
(B)
(C)
(D)
(C)
(A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
DS22077B-page 6
Preliminary
? 2008 Microchip Technology Inc.
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